As a background art in this technical field, there is an interrupt control system disclosed in JP 11-312138 A (PTL 1). This publication describes “to provide an interrupt control system capable of, for example, reducing a load of a CPU, reducing an interrupt detection time, and reducing a wasteful use of a system bus” as an object and describes “each of a plurality of devices 7 to 9 transfers information of an interrupt factor register to a main memory 5 monitored by a CPU 1 by using DMA at the same timing as the timing of an interrupt so that read processing of the interrupt factor register for all the devices, which is executed by the CPU 1, is reduced by one DMA transfer. Therefore, the CPU 1 can quickly recognize interrupt factors of the devices, and, in addition, a processing time can be reduced and the wasteful use of the system bus can be removed, which results in reduction in the loads of the CPU and the system bus.” as solving means (see ABSTRACT).